1. Field of the Invention
The present invention relates to a structure of a high voltage transistor in a semiconductor device and a method of manufacturing the same and, more particularly to a structure of a high voltage transistor in a semiconductor device and a method of manufacturing the same to embody a bootstrap circuit and a flash EEPROM which utilize high voltage.
2. Information Disclosure Statement
Conventional high voltage transistors are classified according to whether they are transistors with a source and drain formed in a DDD (Double Diffused Drain) structure or dough-net type transistors.
FIG. 1 is a sectional view of a conventional dough-net type high voltage transistor and FIG. 2 is a layout of FIG. 1.
Referring to FIGS. 1 and 2, a channel stop region 2 is formed by implanting ion on a silicon substrate 1 on which a field oxide film 3 is to be formed to prevent a parasitic field transistor from causing a malfunction. The field oxide film 3 is formed by LOCOS (Local Oxidation of Silicon) isolation method. First and second gate electrodes 5A and 5B are formed by depositing polysilicon and by etching the polysilicon utilizing a gate electrode mask. The first gate electrode 5A located between a source region 6A and a drain region 6B. The second gate electrode 5B which is formed on a section of the silicon substrate 1 and on a section of the field oxide film 3 along the edge of the field oxide film 3 is connected to the first gate electrode 5A. The second gate electrode 5B functions to prevent a junction breakdown. The source and drain regions 6A and 6B are formed by ion implantation after forming the first and second gate electrodes 5A and 5B. The gate oxide film 4 electrically insulates the silicon substrate 1 from the first and second gate electrodes 5A and 5B. A load oxide film 7 is formed on the entire upper part of the device including on the first and second gate electrodes 5A and 5B to protect the device. As a final step in manufacturing the high voltage transistor, a metal wiring 8 is formed.
In general, the gate oxide film of the high voltage transistor is thick, and in a transistor having a thick gate oxide film as such, the concentration of the channel stop region is relatively higher than that of the channel surface. Thereby, a junction breakdown occurs between the source(or drain) region and the channel stop region. Therefore, a dough-net type transistor can better solve the problem due to the channel stop region of high concentration in comparison with the source and drain region in the conventional simple DDD structure so as to increase the junction breakdown voltage. However, in a VLSI process in which many transistors are arrayed, the second gate electrode 5B must be additionally formed to prevent the junction breakdown between the channel stop region 2 and the source region 6A (or drain region 6B). In adding such second gate electrode 5B, a problem arises with integrating the device. The amount of space taken up by the device is increased because of the area required to form the second gate electrode 5B. Similarly, with transistors in which the source and drain are formed in DDD structure, the relatively large lateral diffusion create a problem with integrating the device.